1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the field of semiconductor memories.
2. Description of the Prior Art
In many circuits, particularly those that run off remote power supplies such as batteries, it is important to keep the power consumption of the circuits low. As well as addressing the issue of operational circuit efficiency attention is also being turned to reducing static power loss, i.e. power loss due to currents occurring while a circuit is not performing operations. One solution to this issue is to simply turn off the supply to a portion of the design that is not currently being used. This serves to save static power, but there are significant dynamic power costs associated with restoring the state of the system when power is once again supplied to that portion of the design. Furthermore, there are additional drawbacks associated with a lag in response time associated with this restoration of state. This may not be acceptable in some systems.
To address these issues there are proposals for building retention flops to retain the state of the logic while a portion of it is powered down. Such a mode of operation allows the stored signal values to be securely held in a small portion of the circuitry whilst the remainder of the circuitry is powered down for power leakage reduction purposes. When power is resumed, the saved signal value is restored and operation continues.
However, much of the state of a system may typically be contained in other semiconductor memory devices such as SRAM array structures. These SRAM arrays due to their size contribute a large percentage of the total static power consumption in a typical SoC. Traditional techniques used to combat this static power consumption in the arrays result in significant performance hits to the read and write timing.
“A read-static-margin-free SRAM cell for low-Vdd and high-speed applications” by Takeda et al from ISSCC 2005, Session 26, static memory 26.3 pages 478 and 479 looks at improving data retention and increasing the speed of data access. It proposes the reduction of the voltage level supplied to a six transistor cell of the SRAM during write to ensure that the write signal is able to switch the state of the cell. It does not address the problem of reducing power consumption.